1. Field of the Invention
The present invention relates to a semiconductor device and a test method thereof, and more particularly relates to a semiconductor device that includes a plurality of core chips and an interface chip for controlling the core chips and a test method thereof.
2. Description of the Related Art
A memory capacity that is required in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) are increasing every year. To satisfy this requirement by increasing a memory capacity of each memory chip prevents to secure a yield rate because it requires finer processing than so far. Therefore, in recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity (see Japanese Patent Application Laid-Open (JP-A) No. 2002-305283). However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device is included in each memory chip. For this reason, it is difficult to greatly increase a memory capacity for each chip.
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there have been a further problem that it is difficult to speed up the front end unit.
As a method to resolve the above problem, a method that detaches the front end unit from each memory chips and integrate them in one interface chip and laminates these chips, thereby constituting one semiconductor memory device, is suggested (see JP-A No. 2007-157266 or JP-A No. 2006-313607). According to this method, with respect to memory chips (Hereafter, a memory chip whose front end unit was detached is called ‘a core chip’.), it becomes possible to increase a memory capacity for each chip because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor memory device that has a large memory capacity and a high operation speed as a whole.
In addition, as a method of testing a semiconductor device, “parallel test” is known which compresses a plurality of items of test data read from a memory array and outputs an obtained test result signal to an outside (see JP-A No. H11-339499). By performing a parallel test, it is possible to reduce a test time.
However, in the above conventional multichip package or a semiconductor device including a plurality of core chips and an interface chip, there has been a problem that it takes a long time to perform a test. This problem is explained in detail below with the latter case as an example.
With a semiconductor device formed with a plurality of core chips and an interface chip, a data terminal of each core chip is commonly connected to the interface chip through silicon vias. The test result signal is also outputted as a type of data, and then is supplied to the interface chip through the above through silicon vias and outputted to an outside through the interface chip. Therefore, with a scheme of outputting a test result signal from a data terminal, it is not possible to output test result signals simultaneously from a plurality of core chips. In this case, the test result signals need to be outputted sequentially from each core chip, thereby increasing the time required for the test.